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CXA1992R
Preliminary RF Signal Processing Servo Amplifier For the availability of this product, please contact the sales office.
Description The CXA1992R is a bipolar IC developed for CD player RF signal processing and servo control. This IC supports three-spot optical system pickups. Features * Automatic focus bias adjustment circuit * Automatic tracking balance and gain adjustment circuits * RF level control circuit * Interruption countermeasure circuit * Sled overrun prevention circuit * Anti-shock circuit * Defect detection and prevention circuits * RF 1-V amplifier, RF amplifier * APC circuit * Focus and tracking error amplifier * Focus, tracking and sled servo control circuits * Focus OK circuit * Mirror detection circuit * Single power supply and dual power supplies Applications CD players Structure Bipolar silicon monolithic IC 52 pin LQFP (Plastic)
Absolute Maximum Ratings (Ta = 25C) 12 V * Supply voltage VCC * Operating temperature Topr -20 to +75 C * Storage temperature Tstg -65 to +150 C * Allowable power dissipation PD 600 mW Recommended Operating Conditions Operating supply voltage VCC - VEE 3.0 to 5.5
V
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
PE96527-ST
CXA1992R
Block Diagram
RF_M
RFTC
RF_O
RF_I
CC1
PD2
39
38
37 VEE
36
35
34
33
32
31
30
29
28
CC2
PD1
LD
CB
27
PD2 IV AMP
PD1 IV AMP
RF SUMMING AMP
FE_BIAS 40 VCC APC IIL VCC TTL
FOK
PD
CP
26 SENS2
F 41 F IV AMP
VEE LASER POWER CONTROL
25 SENS1
E 42 E IV AMP
VCC
FE AMP
VCC 24 C. OUT VEE DFCT
IFB2
IFB3
IFB1
IFB4
IFB5
EI 43 BAL1 BAL2 BAL3 BAL4
IFB6
23 VEE
LEVEL S
XRST
VEE VEE TOG1 TOG2 TOG3 TOG4 VEE 44 TGFL VEE FO. BIAS WINDOW COMP. VCC TEO 45 TRK. GAIN WINDOW COMP. 22 DATA MIRR IIL TTL FOK
TTL IIL
21 XLT
LDON
TGFL
LPCL
TEI 47
ATSC 48 ATSC WINDOW COMP. TZC COMP. TZC 49 DFCT TM1 TDFCT 50 TG1 VCC TRACKING PHASE COMPENSATION
FOH FOL TGH TGL BALH BALL ATSC TZC FZC
LPC
IIL DATA REGISTER INPUT SHIFT REGISTER ADDRESS DECODER SENS SELECTOR OUTPUT DECODER VCC
CC1
LPFI 46
MIRR
DFCT1
E-F BALANCE WINDOW COMP.
20 CLK
19 LOCK
18
VCC
DFCTO
IFB1-6 BAL1-4 TOG1-4
FS1-4
TG1-2
TM1-7
PS1-4 ISET 17 ISET
VCC TM4
VCC 16 TM6 SL_O
VC 51 VCC VCC VEE FZC 52 FOCUS PHASE COMPENSATION FS1 TM3 VEE FS2 DFCT FZC COMP. FS4 Charge up TG2 TM5 VEE TM2 TM7
15
SL_M
14
SL_P
FSET
VEE 1 FEO 2 FEI 3 FDFCT 4 FGD 5 FLB 6 FE_O 7 FE_M 8 SRCH 9 TGU 10 TG2 11 FSET 12 TA_M 13 TA_O
-2-
CXA1992R
Pin Description Pin No. Symbol I/O Equivalent circuit Description
10 25p 147 1 174k 300 10
1
FEO
O
Focus error amplifier output. Connected internally to the window comparator input for bias adjustment.
2
FEI
I
2
147 100k 147
Focus error input.
3
FDFCT
I
3
3
Capacitor connection pin for defect time constant.
4
FGD
I
4
147
68k
Ground this pin through a capacitor for cutting the focus servo highfrequency gain.
4
130k
40k 5
330k 470k
5
FLB
I
External time constant setting pin for boosting the focus servo lowfrequency.
6
FE_O
O
6
Focus drive output.
13
TA_O
O
13 16
Tracking drive output.
16
SL_O
O
250
Sled drive output.
147
90k
7
FE_M
I
7 50k 2
Focus amplifier inverted input.
-3-
CXA1992R
Pin No.
Symbol
I/O
Equivalent circuit
Description
147
8
SRCH
I
8 50k 11
External time constant setting pin for generating focus search waveform.
110k
9
TGU
I
147 20k 9 82k
External time constant setting pin for switching tracking highfrequency gain.
10
TG2
I
10 470k
External time constant setting pin for switching tracking high-frequency gain.
147k
11
FSET
I
11 15k 15k
Peak frequency setting pin for focus and tracking phase compensation amplifier.
100k
12
147
TA_M
I
12 11
Tracking amplifier inverted input.
14
SL_P
I
147 14 2
Sled amplifier non-inverted input.
15
SL_M
I
147 15 22
Sled amplifier inverted input.
-4-
CXA1992R
Pin No.
Symbol
I/O
Equivalent circuit
Description
17
ISET
I
147 17 50
Connect an external capacitance to set the current which determines the Focus search, Track jump, and Sled kick heights.
18
VCC
I
18
VCC
Positive power supply. The sled overrun prevention circuit operates when this pin is Low. (no pull-up resistance) Serial data transfer clock input from CPU. (no pull-up resistance) Serial data input from CPU. (no pull-up resistance)
19
LOCK
I
19 147 1k
20
20
CLK
I
20 22
22
DATA
I
21
XLT
I
147 21 23 2k
20
Latch input from CPU. (no pull-up resistance)
23
XRST
I
5p
Reset input; resets at Low. (no pull-up resistance)
24
C. OUT
O
24 20k 147
Track number count signal output. Outputs FZC, DFCT1, TZC, BALH, TGH, FOH, ATSC, and others according to the command from CPU.
100k
25
SENS1
O
25 26
26
SENS2
O
Outputs DFCT2, MIRR, BALL, TGL, FOL, and others according to the command from the CPU.
20k 147
27
FOK
O
27
40k
Focus OK comparator output.
100k
-5-
CXA1992R
Pin No.
Symbol
I/O
Equivalent circuit
Description
28
CC2
I
147 30 147 29
Input for the defect bottom hold output with capacitance coupled.
29
CC1
O
Defect bottom hold output. Connected internally to the interruption comparator input.
147 120k 28 11k 43k
30
CB
I
Connection pin for defect bottom hold capacitor.
31 100k
31
CP
I
1.5k
Connection pin for MIRR hold capacitor. MIRR comparator non-inverted input.
32
RF_I
I
Input for the RF summing amplifier output with capacitance coupled.
147
33
RF_O
O
32
RF sunning amplifier output. Eyepattern check point.
147 33 147 34 10k 10k
34
RF_M
I
RF summing amplifier inverted input. The RF amplifier gain is determined by the resistance connected between this pin and RFO pin.
35
RFTC
I
147 35 50
50
External time constant setting pin during RF level control.
10
-6-
CXA1992R
Pin No.
Symbol
I/O
Equivalent circuit
Description
10k 1k
36
LD
O
36
APC amplifier output.
20 8 147 37 10k 55k
37
PD
I
APC amplifier input.
10k 2k
8k
38 39
PD1 PD2
I I
147 38 39 100 11.6k
RF I-V amplifier inverted input. Connect these pins to the photo diode A + C and B + D pins.
4k
147
40
FE_BIAS
I
40 6
Bias adjustment of focus error amplifier. Leave this pin open for automatic adjustment.
12p 260k
41 42
F E
I I
147 41 42 10 500
F I-V and E I-V amplifier inverted input. Connect these pins to photo diodes F and E.
-7-
CXA1992R
Pin No.
Symbol
I/O
Equivalent circuit
Description
6.8k 110k 56k 27k 13k
43
EI
--
147 43
260k 75k
I-V amplifier E gain adjustment. (When not using automatic balance adjustment)
44
VEE
--
44
VEE
Negative power supply.
147
45
TEO
O
45
7.5k 16k 7.5k 3.3k 1.5k 150k 10k 150k
Tracking error amplifier output. E-F signal is output.
147
46
LPFI
I
46
Comparator input for balance adjustment. (Input from TEO through LPF)
7
47
TEI
I
47
147
100k
Tracking error input.
147
50
TDFCT
I
50
3
Capacitor connection pin for defect time constant.
-8-
CXA1992R
Pin No.
Symbol
I/O
Equivalent circuit
Description
1k 147
100k
48
ATSC
I
48 100k 10 10 1k
Window comparator input for ATSC detection.
10 147
49
TZC
I
49 75k
Tracking zero-cross comparator input.
51
VC
O
50 51
120
(VCC + VEE)/2 direct voltage output.
120
VC
10 147
51k
52
FZC
I
52 75k 9k
Focus zero-cross comparator input.
-9-
CXA1992R
Electrical Characteristics
TEST T1 T2 T3 T4 RF amplifier T5 T6 T7 T8 T9 T10 T11 T12 T13 FE amplifier T14 T15 T16 T17 T18 T19 T20 Item Current consumption 1 Current consumption 2 SW conditions (ON switches) 51 51 SD RST RST RST RST 33S, 38, 39 RST RST RST 39F 39F 39F 39F 39F 39F 3BF 3BE 3BD 3BB 3B7 3AF 39F 39 38 1 1 1 1 1 1 1 1 1 38 39 38 39 38 39 38 39 Input pin 18 44 -- Measurement pin 18 44 51 33 33 33 33 1 1 1
(VCC = 1.5V, VEE = 1.5V, Topr = 25C)
Measurement conditions Min. 16.8 Typ. 24.0 Max. 31.2 Unit mA mA mV mV dB V V mV dB dB dB V V mV mV dB dB dB dB dB
-31.2 -24.0 -16.8 -100 -50 1kHz I/O ratio V2 = 0.2VDC V2 = 0.2VDC 1FB6: ON 1kHz I/O ratio 1kHz I/O ratio 25.1 1.2 -- -120 27 27 -3 V2 = 100mVDC V2 = 100mVDC IFB1, 2, 3, 4, 5, 6: OFF IFB1: ON, BIAS0: reference
IFB2: ON, BIAS0: reference Output gain difference with T15 IFB3: ON, BIAS0: reference Output gain difference with V17 IFB4: ON, BIAS0: reference Output gain difference with V18 IFB5: ON, BIAS0: reference Output gain difference with V19 IFB6: ON, BIAS0: reference Output gain difference with V20
Center amplifier 51, 51D output offset Offset Voltage gain
0 0 28.1
100 50 31.1 -- -0.3
Max. output 33D, 38 amplitude - High Max. output amplitude - Low Offset 33D, 39 1D
0 30 30 0 1.3 -1.3 801 -25 6 6 6 6 6
120 33 33 3 -- -1 1042
Voltage gain 1 1S, 38 (PHD1) Voltage gain 2 1S, 39 (PHD2) Voltage gain difference 1S
Max. output 1D, 39 voltage - High Max. output voltage - Low BIAS0 BIAS1 BIAS2 BIAS3 BIAS4 BIAS5 BIAS6 1D, 38 1D 1D 1D 1D 1D 1D 1D
1 -- 560
- 10 -
CXA1992R
TEST
Item
SW conditions (ON switches)
SD
Input pin 40
Measurement pin 1
Measurement conditions IFB6: ON
Pin 1 voltage when SENS1 (Pin 25) goes from High to Low IFB6: ON
Min.
Typ.
Max.
Unit
T21
FE amplifier
FOH threshold 1D, 25D, 40
39F
20
mV
T22
FOL threshold 1D, 26D, 40
39F 34F 308 36F 308 36F 308 34F 34E 30F 34D 34B 347 34F 30F 00 30E 30D 30B 307 34F 308 34F 308 3C4 3C4 3C4 3C4 3C0
40 41 42 41 42 41 41 41 41 41 42 42 42 42 42 41 42 37 37 37 37 37
1
Pin 1 voltage when SENS2 (Pin 26) goes from High to Low
-20
mV
T23 T24 T25 T26 T27 T28 T29 TE amplifier T30 T31 T32 T33 T34 T35 T36 T37 T38 T39 APC T40 T41 T42
Offset GAIN UP (F) GAIN UP (E) Voltage gain F0 Voltage gain F1 Voltage gain F2 Voltage gain F3 Voltage gain F4 Voltage gain E0 Voltage gain E1 Voltage gain E2 Voltage gain E3 Voltage gain E4
45D 41, 45S 42, 45S 41, 45S 41, 45S 41, 45S 41, 45S 41, 45S 42, 45S 42, 45S 42, 45S 42, 45S 42, 45S
45 45 45 45 45 45 45 45 45 45 45 45 45 45 45 36 36 36 36 36
TOG: OFF, BAL1, 2, 3: ON V1 = 2 kHz, I/O ratio TOG: OFF, BAL1, 2, 3: ON V1 = 2 kHz, I/O ratio TOG: OFF, BAL1, 2, 3: ON V1 = 2kHz, TOG: OFF I/O ratio V1 = 2kHz, TOG1: ON Reference to F0 V1 = 2kHz, TOG2: ON Reference to F0 V1 = 2kHz, TOG3: ON Reference to F0 V1 = 2kHz, TOG4: ON Reference to F0 V1 = 2kHz, BAL: OFF I/O ratio V1 = 2kHz, BAL1: ON Reference to E0 V1 = 2kHz, BAL2: ON Reference to E0 V1 = 2kHz, BAL3: ON Reference to E0 V1 = 2kHz, BAL4: ON Reference to E0 V1 = 1VDC, TOG: OFF, BAL1, 2, 3: ON V1 = 1VDC, TOG: OFF, BAL1, 2, 3: ON I37 = 364A I37 = 439A I37 = 515A 0.8mA sink I37 = 515A, LD: OFF
-25 8.6 8.6 2.5 -2.6 -4.4 -7.7
0 11.6 11.6 5.5 -2.1 -3.9 -7.2
25 14.6 14.6 8.5 -1.6 -3.4 -6.7
mV dB dB dB dB dB dB dB dB dB dB dB dB V V mV mV mV
-12.2 -11.7 -11.2 -0.33 2.67 0.17 0.6 1.46 3.03 0.5 -- -704 -233 669 0 1.1 1.3 500 -- 0.47 0.9 1.76 3.33 5.67 0.77 1.2 2.06 3.63 -- -0.5
Max. output 41, 45D voltage - High Max. output voltage - Low 42, 45D
Output voltage 36D, 37 1 Output voltage 36D, 37 2 Output voltage 36D, 37 3 Output voltage 36, 36D 4 LD OFF 36, 36D, 37
mV V
- 11 -
CXA1992R
TEST T43 T44 T45 T46 T47 T48 T49 Focus servo T50 T51 T52 T53 T54 T55 T56 T57 T58 Tracking servo T59 T60 T61 T62 T63 T64
Item 30% limit 10% limit -30% limit -10% limit Direct voltage gain FCS total gain Feed through 1
SW conditions (ON switches) 32, 36D, 37 32, 36D, 37 36D, 37, 38, 39 36D, 37, 38, 39 2, 6D
SD 3C7 3C5 3C7 3C5 08 --
Input pin 37 32 37 32 37 38 39 37 38 39 2 -- 2 52 2 2 -- -- 47 -- 47 47 47
Measurement pin 36 36 36 36 6 -- 6 52 6 6 6 6 13 -- 13 13 13 13 13
Measurement conditions
I37 = 439A Output difference with T39 I37 = 439A Output difference with T39 I37 = 515A Output difference with T40 I37 = 515A Output difference with T40
Min.
Typ. 1304 470 -1307 -466
Max.
Unit mV mV mV mV
RF AGC
18 T9 + T47
Output gain difference between SD = 00 and SD = 08. Pin 52 voltage when SENS1 (Pin 25) goes from Low to High
21 51 -- 221 1.3 -1.3
24 53 -30 261 -- -1
dB dB dB mV V V mV mV dB dB dB V V mV mV mV mV mV
49 -- 181 1 --
2, 6S
00 08 00 08 08 02 03 25 --
FZC threshold 26D, 52 Max. output 2, 6D, 6S voltage - High Max. output voltage - Low Search voltage (-) Search voltage (+) Direct voltage gain TRK total gain Feed through 1 13S, 47 2, 6D, 6S 6D 6D 13D, 47
V1 = 200mVDC V1 = -200mVDC
-640 -500 -360 360 12.2 T26 + T55
Output gain difference between SD = 20 and SD = 25.
500 14.6 20.1 -- 1.3 -1.3
640 17.6 22.1 -39 -- -1
18.1 -- 1 --
20 25 20 25 20 25 2C 28 10 10 20
Max. output 13D, 47 voltage - High Max. output voltage - Low Jump output voltage (-) Jump output voltage (+) ATSC threshold (-) ATSC threshold (+) TZC threshold 13D, 47 13D 13D 10, 10D, 48 10, 10D, 48 25D, 49, 49B
V1 = -0.5VDC V1 = 0.5VDC
-640 -500 -360 360
Input voltage when TG2 (Pin 10) goes from Vcc/2 to Vcc Input voltage when TG2 (Pin 10) goes from Vcc/2 to Vcc
500 -15 15 0
640 -7 25 20
48 48 49
48 48 49
-25 7 -20
Pin 49 voltage when SENS1 (Pin 25) is 0V
- 12 -
CXA1992R
TEST T65 Tracking servo T65 T67 T68 FOK T69 T70 T71 Sled servo T72 T73 T74 T75 T76 MIRROR T77 T78 T79 T80 T81 T82
Item
SW conditions (ON switches)
SD 300 300 340 340 -- 25 20 25 25 25 20 20 20 20 20 10 10 10 10
Input pin 46 46 45 45 32 14 14 14 14 -- -- 32 32 32 38 39 38 39 38 39 38 39
Measurement pin 46 46 45 45 32 16 16 16 16 16 16 26 26 26 25 25 25 25
Measurement conditions
Pin 46 voltage when SENS1 (Pin 25) goes from High to Low Pin 46 voltage when SENS2 (Pin 26) goes from High to Low Pin 45 voltage when SENS1 (Pin 25) goes from High to Low Pin 45 voltage when SENS2 (Pin 26) goes from Low to High
Min.
Typ. 20 -20 400 300 -367
Max.
Unit mV mV mV mV mV
BAL COMP 25D, 46, threshold - High 46B BAL COMP 26D, 46, threshold - Low 46B GAIN COMP 25D, 45, threshold - High 45D GAIN COMP 26D, 45, threshold - Low 45D FOK threshold Voltage gain Feed through 27D, 32 14, 14B, 15, 16S 14, 14B, 16S
Pin 32 voltage when Pin 27 is 0V V1 = 100 Hz, I/O ratio
Output gain difference between SD = 20 and SD = 25.
50 -- 1 --
-- -- 1.3 -1.3
-- -34 -- -1
dB dB V V mV mV kHz Vp-p Vp-p kHz kHz Vp-p Vp-p
Max. output 14, 14B, voltage - High 16D Max. output voltage - Low Kick voltage 1 Kick voltage 2
Max. operating frequency 1
Min. input operating voltage 1 Max. input operating voltage 1
V1 = 400mVDC V1 = 400mVDC REV x 1 FWD x 1 Measures at SENS2 pin. Measures at SENS2 pin. Measures at SENS2 pin. Measures at SENS1 pin. Measures at SENS1 pin. Measures at SENS1 pin. Measures at SENS1 pin.
14, 14B, 16D 16D 16D 26S, 32 26S, 32 26S, 32 25S, 38, 39 25S, 38, 39 25S, 38, 39 25S, 38, 39
-750 -600 -450 450 30 -- 1.8 -- 2.5 -- 1.8 600 -- -- -- -- -- -- -- 750 -- 0.3 -- 1 -- 0.5 --
Min. operating frequency 1
DEFECT
Max. operating frequency 1
Min. input operating voltage 1 Max. input operating voltage 1
- 13 -
Electrical Characteristics Measurement Circuit
STORAGE2 GND DC OUTPUT GND
VCC
GND I37 0mA R24 10k GND GND S33D S33S R15 1M C5 0.1 S36 S36D R17 22k R48 10k GND S26S S26D SENS2 26 S25S S25D SENS1 25 S24S S24D C. OUT 24 R38 10k R45 10k R39 10k R46 10k R51 100 R40 10k R52 100 R47 10k R53 100 GND 33 30 29 CC1 CC2 FOK CB 28 27 RF_O RF_I CP 32 31 35 34 RF_M RFTC S27D S32 S27S STORAGE1 C6 3300p C7 1000p C9 3300p R54 100 S28 R11 10k S38 S37 R12 R14 330 10k R31 100k R35 10k I36 0mA R18 10k GND R21 100
VEE
V2
R9 10k
AC
S39
DC 39 PD2 PD1 PD LD 38 36 37
I40 0mA
S40
40 FE_BIAS
R6 390k
S41
41 F
R5 390k
S42
42 E
R4 13k XRST 23
S43
43 EI
XRST
C2 33 DATA 22 DATA
44 VEE
A44 XLT 21
R2 100
S45 XLT
S45S
S45D CLK 20
45 TEO
FE_O
FLB
FGD
FDFCT
FEI
FEO
FE_M
SRCH
TGU
TG2
FSET
TA_M
TA_O
- 14 -
LOCK 19 S19 VCC 18 S17 ISET 17 R37 120k SL_O 16 R36 60k SL_M 15 S16 SL_P 14 S14 S14B C10 33 R43 120k S16D S16S R42 R41 13k 10k 1 2 3 7 4 8 5 6 9 10 11 12 13 S1S S2 S3 S4 C4 1000P R13 47k R23 200k S6S S8D S6D S13D R16 13k A3 S5 R20 100k S7 S9 R28 510k S10 S10D R27 10k R30 100k S13S R33 200k C8 0.01 S12 C3 1000P R34 13k R10 100 R19 100 R22 10k R25 10k R26 10k R29 10k R32 100
R1 10k
S46 CLK
S46B
46 LPFI
A46
S47 D_GND
47 TEI
S48 A18 R50 10k R49 100
48 ATSC
S49
S49B
49 TZC
A49
A50
S50
C1 1000P
50 TDFCT
S51
R44 5.1k C11 47 S15
R3 10k
I51 0mA
S51I
51 VC
S51D
S52
52 FZC
A14
V1
S1D
AC
DC
R8 10k
CXA1992R
GND
R7 10k
CXA1992R
Application Circuit 1 (2.5V power supply)
Vcc 1k A C VEE B D 39 38 37 36 35 34 33 32 500 100 3.3 Vcc 1 22 100
LD 10H PD VEE VEE MICRO COMPUTER DSP 27
1M
1
22k 0.01
0.033
0.033
31
0.01
30
29
28
RF_M
RF_O
PD
CP
CC1
RFTC
RF_I
40 F E
FOK
SENS2
PD1
LD
CC2
PD2
CB
FE_BIAS
26
41 F 42 E 43 EI
SENS1 25 C. OUT 24 XRST 23 DATA 22 XLT 21 CLK 20 LOCK 19 Vcc 18 60k ISET 17 Vcc VEE
VEE
44 VEE 45 TEO
100k 0.01 0.047 330k
150k 46 LPFI 0.01 47 TEI 47k 48 ATSC 470p 49 TZC
0.1 51 VC SL_M 15 FZC
FDFCT
0.015 8.2k 3.3
SRCH
TA_M
FE_O
FE_M
FSET
TA_O
FGD
TGU
FEO
TG2
FEI
FLB
52 0.022
SL_P 14
1
2
10k 10k 2200p
4.7 100k 0.033 510k Vcc
100k 0.015 DRIVER
0.1 0.1
DRIVER
Application Circuit 2 (Single +5V power supply)
Vcc 1k A C 3.3 Vcc 1 22 100
LD 10H PD
1M
B D 39
500
1
100
82k
4 3 680k
5
6 0.1
7
8
9
10
11
12
13 22 15k
100k
0.022
50 TDFCT
SL_O 16
DRIVER
0.033
22k 0.01
0.033
38
37
36
35
34
33
32
31
0.01
MICRO COMPUTER DSP 27
30
29
28
RF_M
RF_O
PD
CP
CC1
RFTC
RF_I
40 F E
FOK
SENS2
PD1
LD
CC2
PD2
CB
FE_BIAS
26
41 F 42 E 43 EI 44 VEE 45 TEO
SENS1 25 C. OUT 24 XRST 23 DATA 22 XLT 21 CLK 20 LOCK 19 Vcc 18 60k ISET 17 Vcc
100k 0.01 0.047 330k 0.022 VCC
150k 46 LPFI 0.01 47 TEI 47k 48 ATSC 470p 49 TZC 0.1 10 50 TDFCT 51 VC
SL_M 15
100k 82k
SL_O 16
DRIVER 0.015 8.2k
SRCH
TA_M
FE_O
FSET
FGD
TGU
FEO
TG2
FEI
FLB
10
FE_M
TA_O
52
FZC
FDFCT
SL_P 14 3.3 22 15k
0.022
1 10k 10k
2
2200p
4 3 680k
5
6
7
8
9 4.7
10
11
12
13
100k 0.033 510k Vcc 0.015 DRIVER
0.1 0.1 0.1 100k DRIVER
Application circuits shown are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits or for any infringement of third party patent and other right due to same.
- 15 -
CXA1992R
Description of Functions RF Amplifier The photo diode currents input to the input pins (PD1 and PD2) are each I-V converted through a 58k equivalent resistor by the PD I-V amplifiers. These signals are added by the RF summing amplifier, and the photo diode (A + B + C + D) current-voltage converted voltage is output to the RFO pin. An eye-pattern check can be performed at this pin.
1k 3.3 34 58k C PD1 iPD1 B PD2 iPD2 39 PD2 IV AMP VC VB 10k 38 PD1 IV AMP VC 58k VC D VA 10k
22k RF_M A 33 RF_O
RF SUMMING AMP
The low frequency component of the RFO output voltage is VRFO = 2.2 x (VA + VB) = 127.6k x (iPD1 + iPD2).
- 16 -
CXA1992R
Focus Error Amplifier
R3 58k R5 32k
R7 174k VB
PD2 39 B+D
1 PD2 IV AMP VC R2 58k R4 32k FE AMP 2
FEO R10 10k FEI R9 10k C1 2200p GND
PD1 38 A+C
VA PD1 IV AMP VC VCC
R6 174k R1 4k 7 R8 100k 6 FE_O FE_M
GND
x1 x2 EF_BIAS 40
x4
x8 x16 x32 VC
FOCUS PHASE COMPENSATION
R11 100k DRIVER
IFB3
IFB5
IFB2
IFB1
IFB4
IFB6
VIN > VH L VIN < VH H 25mV/STEP RESET : IFB1 to IFB6 ON VEE 20mV VIN VC FOL VL VIN > VL H VIN < VL L -20mV VC VH FOH
VC 25 SENS1
SENS SELECTOR
26 SENS2
The focus error amplifier calculates the difference between output VA and VB of the RF I-V amplifier, and output current-voltage converted voltage of the photo diode (A + C - B - D). The FEO output voltage: VFEO = = 174k (VA - VB) 32k 174k {(-58k x iPD1) - (-58k x iPD2)} 32k
= 315.4k (iPD2 - iPD1)
The focus error amplifier has a built-in bias adjustment circuit to enable software-based automatic adjustment. The focus bias adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and OFF. The 6-bit focus bias adjustment switches are controlled with commands. IFB1 to IFB6 are all ON after a reset. The voltage is varied by approximately 25mV per step.
- 17 -
CXA1992R
* Focus error amplifier offset adjustment (when adjusting the IC offset) The offset adjustment is performed by comparing the FEO when the focus servo is OFF with the reference level. The FEO and reference level are compared by the window comparator, and the comparison results are output from SENS1 and SENS2. (ADDRESS D11001110D6) Adjust the offset so that SENS1 and SENS2 are both High. Set the reference level to the center 20mV. 25mV < 40mV < 50mV
Reference level width Variable voltage per step Variable voltage per 2 steps
* Focus bias fine adjustment Fine adjustment is performed by turning the focus bias adjustment switches (IFB1 to IFB6) ON and OFF while monitoring a DSP jitter meter with the microcomputer. The 6-bit focus bias adjustment switches are controlled with commands. * When performing conventional focus bias adjustment Fix the focus bias adjustment switches to the desired settings. (for example, IFB6 ON) In this condition, adjust the focus bias by turning a volume connected to FE_BIAS (Pin 40). [Example circuit]
VCC
Volume 47k 3.9k
40 FE_BIAS
VEE
- 18 -
CXA1992R
Tracking Error Amplifier
R23 100k C3 0.01 R24 150k C4 0.01
TEO 45 R2 260k C2 12p F 41 VF VC F I-V AMP R5 13k R3 26k VC R8 17k R4 6.8k R13 13k V R12 96k VC VE VC E I-V AMP TE AMP R16 NORMAL 96k R14 13k TGFL R9 17k GAIN UP GAIN UP TGFL NORMAL R18 7.5k
GND
GND 46
LPFI VIN > VH L VIN < VH H VH BALH 25 BALL - SENS1
20mV VC VIN VL
+ R22 1.5k VC
E 42
C1 12p
TOG1
TOG2
TOG3
TOG4
R17 10k R19 16k R20 7.5k R21 3.3k
R1 260k
VIN > VL H -20mV VIN < VL L SENS VIN > VH L SELECTOR VIN < VH H VH TGH 400mV SENS2 VIN TGL VL 26
VC
CPU
R6 75k R7 BAL1 110k R10 BAL2 56k R11 BAL3 27k R15 BAL4 13k
VC
300mV RE VC
VIN > VL H VIN < VL L 23 COMAND COMAND CONTROL CONTROL 22 21 20 XRST DATA XLT CLK
VC
43 EI
The difference between E I-V amplifier output VE and F I-V amplifier output VF is taken and output from TEO. The tracking error amplifier has built-in balance and gain adjustment circuits to enable software-based automatic adjustment. The balance adjustment is performed by varying the combined resistance value of the T-configured feedback resistance at the E I-V amplifier. E I-V AMP feedback resistance = R1 + R4 + R1 x R4 RE E I-V AMP feedback resistance = R2 + R5 + R2 x R5 = 403k R3 Vary the combined resistance value of the E I-V amplifier's feedback resistance by using the balance adjustment switches (BAL1 to BAL4). The gain adjustment is performed by resistance dividing the TE AMP output by the gain adjustment switches (TOG1 to TOG4). The balance and gain adjustment switches are controlled with commands. Set the cut-off frequency of the external LPF between 10Hz to 100Hz.
- 19 -
CXA1992R
* Balance adjustment The balance adjustment is performed by passing the tracking error signal (TEO signal) through the external LPF, extracting the offset DC, and comparing it to the reference level. However, the TEO signal frequency distribution ranges form DC to 2kHz. Merely sending the signal through the LPF leaves lower frequency components, and the complete offset DC can not be extracted. To extract it, monitor the TEO signal frequency at all times, and perform adjustment only when a frequency that can lower a sufficient gain appears on the LPF. Use the C.OUT output to check this frequency. The offset DC and reference level are compared by the window comparator. The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001100D6) Adjust the balance so that the SENS1 and SENS2 pins are both High. VIN < VL < VH SENS1 pin BALH SENS2 pin BALL H L VL < VIN < VH H H VL < VH < VIN L H
VH: High level threshold value VIN: Window comparator input signal VL: Low level threshold value
* Gain adjustment Gain adjustment is performed by passing the TEO signal through the HPF and comparing the AC component to the reference level. The AC component is generated by taking the difference between TE and the offset DC input to Pin 46. The AC component and reference level are compared by the window comparator. The comparison signal is output from the SENS1 and SENS2 pins. (ADDRESS D11001101D6) The comparison signal is as follows.
(1) (2) (3)
VH VL VIN SENS1 pin TGH SENS2 pin TGL H H
L
The gain should be adjusted so that the SENS1 and SENS2 pins are as shown in status (2). When the TEO signal level is low and TGH (SENS1 pin) does not go Low, the gain should be raised with the TGFL command for adjustment. If the adjustment does not bring the result of Low, check the pulse duty of TGL (SENS2 pin).
- 20 -
CXA1992R
APC & Laser Power Control
VCC
R1 22
C2 100 LD 36
R6 1k
VCC LDON
L1 10H
130mV PD 37 R8 10k
R10 56k
C1 1
R2 500 LD PD
R3 100 R4 10k R5 55k R11 10k VL R14 5.3k R12 56k VREF VEE
GND VEE VEE
LPC ON/OFF 30%/10%
RF_I
32
1.1Vpp
C3 0.01 RF_O 33
R7 1.47V 39.5k R9 23.5k VC
670mV
VC
RF
35
R13 1M VEE VEE
* APC When the laser diode is driven by a constant current, the optical power output has extremely large negative temperature characteristics. The APC circuit is used to maintain the optical power output at a constant level. The laser diode current is controlled according to the monitor photo diode output. * Laser power control The RF level is stabilized by attaching an offset to the APC VL and controlling the laser power in sync with the RF level fluctuations. The RF_O and RF_I levels are compared and the larger of the two is smoothed by the RFTC's external CR. This signal is then compared with the reference level. The laser power is controlled by attaching an offset to VL according to the results of comparison with the reference level. Set the reference level to 670mV. (center voltage reference) LPC ON/OFF and LD ON/OFF control is performed with commands. The laser power control limit can also be switched between 10% and 30% with commands. LPC OFF ON ON LPCL -- 30% 10% VL variable range Approximately 1.27V Approximately 1.27V 265mV Approximately 1.27V 88mV - 21 -
RFTC
C4 1
CXA1992R
Center Voltage Generation Circuit (The figure below shows a single voltage application; Connect to GND for dual power supplies.) Maximum current is approximately 3mA. Output impedance is approximately 50.
VCC VCC
30k VC 50 51
VC
30k
VEE Connected internally to the VEE pin.
GND
- 22 -
CXA1992R
Focus Servo
9k 0.022 52 FEO 1 10k 2 10k 2200p 3 0.1 FDFCT FGD 4 680k 40k 0.1 ISET 17 50k FS2 FLB 5 0.1 FSET 11 510k 0.015 4.7 8 SRCH FS1 Charge up 60k 11 22 50k FE_M 7 100k FEI 100k DFCT FS3 FS4 68k Focus 100k phase Compensation FE_O 6 FE 75k FZC 51k FZC SENS SELECTOR 25 SENS1
FOCUS COIL
The above figure shows a block diagram of the focus servo. Ordinarily the FE signal is input to the focus phase compensation circuit through a 68k resistance; however, when DFCT is detected, the FE signal is switched to pass through a low-pass filter formed by the internal 100k resistance and the capacitance connected to Pin 3. When this DFCT prevention circuit is not used, leave Pin 3 open. The defect switch operation can be enabled and disabled with command. The capacitor connected between Pin 5 and GND is a time constant to boost the low frequency in the normal playback state. The peak frequency of the focus phase compensation is approximately 1.2kHz when a resistance of 510k is connected to Pin 11. The focus search height is approximately 1.1Vp-p when using the constants indicated in the above figure. This height is inversely proportional to the resistance connected between Pin 17 and VEE. However, changing this resistance also changes the height of the track jump and sled kick as well. The FZC comparator inverted input is set to 15% of Vcc and VC (Pin 51); (Vcc - VC) x 15%. 510k resistance is recommended for Pin 11.
- 23 -
CXA1992R
Tracking and Sled Servo
TE
+
45 TEO
-
TGH GAIN TGL WINDOW COMPARATOR BALH BALANCE WINDOW COMPARATOR BALL
SENS SELECTOR
26 SENS2 25 SENS1
100k
150k
BUFFER AMP 46
47k SLED ON/OFF CONTROL 19 LOCK SLED MOTOR
0.01
0.01
LPFI
SL_O 16 TEI 47 100k TDFCT 50 100k 680k 66p TM6 22A DFCT TM1 680k TG1 SL_M 15
M
0.015
3.3 22 15k
0.1
TM5 ATSC 1k 1k ATSC 48
TM2 22A 14
SL_P
0.047 47k
330k
470p
0.022 49
TZC TZC 9 TGU TG2 TG2 470k
100k
TM4 11A TM3 11A 90k
82k TA_M 12 100k
20k
0.033 10
Tracking Phase Compensation
10k
TA_O TM7
13
FSET 11 510k 0.015
The above figure shows a block diagram of the tracking and sled servo. The capacitor connected between Pins 9 and 10 is a time constant to cut the high-frequency gain when TG2 is OFF. The peak frequency of the tracking phase compensation is approximately 1.2kHz when a 510k resistance is connected to Pin 11. In the CXA1992R, TG1 and TG2 are inter-linked switches. To jump tracks in FWD and REV directions, turn TM3 or TM4 ON. During this time, the peak voltage applied to the tracking coil is determined by the TM3 or TM4 current and the feedback resistance from Pin 12. To be more specific, Track jump peak voltage = TM3 (or TM4) current x feedback resistance value The FWD and REV sled kick is performed by turning TM5 or TM6 ON. During this time, the peak voltage applied to the sled motor is determined by the TM5 or TM6 current and the feedback resistance from Pin 15; Sled kick peak voltage = TM5 (or TM6) current x feedback resistance The values of the current for each switch are determined by the resistance connected between Pin 17 and VEE. When this resistance is 60k : TM3 (or TM4) = 11A, and TM5 (or TM6) = 22A. As is the case with the FE signal, the TE signal is switched to pass through a low-pass filter formed by the internal resistance (100k) and the capacitance connected to Pin 50. - 24 -
120k
8.2k
TRACKING COIL
CXA1992R
The ISET pin is used to connect external resistance. This external resistance sets the current which determines the focus search, track jump, and sled kick heights. * Focus search current I1 =
I1 I2
VBG x R
1 2
(VBG: approximately 1.27V)
I2 = 2I1
FS1
* Track jump current (TM3 and TM4 current) I= VBG x R 1 2
* Sled kick current (TM5 and TM6 current, when D1 = D0 = 0 during 1X$ commands) I= VBG R
Use external resistance of between 30k to 240k. Using external resistance outside this range may cause oscillation.
- 25 -
CXA1992R
Focus OK Circuit
RF VCC
RF_O C5 0.01 RF_I 33
x1
20k 54k 27 FOK 92k 0.63V
32 15k
VG
FOCUS OK AMP
FOCUS OK COMPARATOR
The focus OK circuit creates the timing window okaying the focus servo from the focus search state. The HPF output is obtained at Pin 32 from Pin 33 (RF signal), and the LPF output (opposite phase) of the focus OK amplifier output is also obtained. The focus OK output is inverted when VRFI - VRFO -0.37V. Note that, C5 determines the time constant of the HPF for the mirror circuit and the LPF of the focus OK amplifier. Ordinarily, with a C5 equal to 0.01F selected, the fc is equal to 1kHz, and block error rate degradation brought about by RF envelope defects caused by scratched discs can be prevented. Defect Circuit After the RFI signal is reverted, two time constants, long and short, are held at bottom. The short time constant bottom hold responds to 0.1ms or greater disc mirror defects, and the long time constant bottom hold holds the pre-defect mirror level. By differentiating and level-shifting these constants with capacitor coupling and comparing both signals, the mirror defect detection signal is generated.
0.033 CC1 29 CC2 28 FLIP FLOP RF_O 33 a
x2
DFCT2 26 SENS2
b
c
e SENS SELECTOR
25 SENS1
DEFECT AMP
d DFCT1 DEFECT SW 30 0.01 DEFECT BOTTOM HOLD DEFECT COMPARATOR
CB
a
RFO
b
DEFECT AMP BOTTOM HOLD (1) solid line CC1 H DFCT1 L
c
d
BOTTOM HOLD (2) dotted line CC2
e
- 26 -
CXA1992R
Mirror Circuit The mirror circuit performs peak and bottom hold after the RFI signal has been amplified. The peak and bottom holds are both held through the use of a time constant. For the peak hold, a time constant can follow a 30kHz traverse, and, for the bottom hold, one can follow the rotation cycle envelope fluctuation.
RF_O 33 RF
MIRROR HOLD AMP 0.033 PEAK & BOTTOM HOLD H
x1
32 RF_I
31 CP J MIRR SENS SELECTOR MIRROR COMPARATOR 26 SENS2 K
x 1.4
G MIRROR AMP
I
RF_O 0V
G (RF_I)
0V
H (PEAK HOLD)
0V
I (BOTTOM HOLD) J K (MIRROR HOLD)
0V
MIRR
H L
The DC playback envelope signal J is obtained by amplifying the difference between the peak and bottom hold signals H and I. Signal J has a large time constant of 2/3 its peak value, and the mirror output is obtained by comparing it to the peak hold signal K. Accordingly, when on the disc track, the mirror output is Low; when between tracks (mirrored portion), it is High; and when a defect is detected, it is High. The mirror hold time constant must be sufficiently large compared with the traverse signal. In the CXA1992R, this mirror output is used only during braking operations, and no external output pin is attached. Accordingly, when connecting DSP with MIRR input pin, input the C.OUT output to the MIRR input of the DSP. - 27 -
CXA1992R
SENS Selector
FZC DFCT1 TZC BALH 25 SENS1 TGH FOH ATSC
HIGH-Z DFCT2 MIRR BALL 26 SENS2 TGL FOL
What is output to the SENS1 and SENS2 pins varies according to the address input to the DATA pin. DATA (Pin 22) 8-bit transfer ADDRESS D7 0 0 0 0 1 D6 0 0 0 1 1 D5 0 0 1 0 1 D4 0 1 0 0 1 D3 X X X X X DATA D2 X X X X X D1 X X X X X D0 X X X X X FZC DFCT1 TZC H (HIGH-Z) H (HIGH-Z) DFCT2 MIRR H (HIGH-Z) SENS1 SENS2
DATA (Pin 22) 12-bit transfer ADDRESS D11 D10 0 0 0 0 0 0 0 0 D9 1 1 1 1 D8 1 1 1 1 D7 0 0 1 1 D6 0 1 0 1 D5 X X X X D4 X X X X DATA D3 X X X X D2 X X X X D1 X X X X D0 X X X X BALH TGH FOH ATSC BALL TGL FOL H (HIGH-Z) SENS1 SENS2
Notes) * 12-bit transfer should be performed during $3XX commands. When 8 bits are transferred, SENS1 and SENS2 are switched according to the D3 and D2 data. * SENS1 and SENS2 are switched without latching.
- 28 -
CXA1992R
Commands The input data to operate this IC is configured as 8-bit/12-bit data; however, below, this input data is represented by 2-digit hexadecimal numerals in the form $XX, where X is a hexadecimal numeral between 0 and F/$XXX for 12-bit. Commands for the CXA1992R can be broadly divided into four groups ranging in value from $0X, $1X, $2X, $3XX. 1. $0X (FZC at SENS1 pin (Pin 25), H (Hi-Z) at SENS2 pin (Pin 26)) These commands are related to focus servo control. The bit configuration is as shown below. D7 0 D6 0 D5 0 D4 0 D3 FS4 D2 -- D1 FS2 D0 FS1
Four focus related switches exist: FS1, FS2, FS4 and DFCT. $00 $02 When FS1 = 0, Pin 8 is charged to (22A - 11A) x 50k = 0.55V. If, in addition, FS2 = 0, this voltage is no longer transferred, and the output at Pin 6 becomes 0V. From the state described above, the only FS2 becomes 1. When this occurs, a negative signal is output to Pin 6. This voltage level is obtained by equation 1 below. (22A - 11A) x 50k x resistance between Pins 6 and 7 .... Equation 1 50k
$03
The SRCH DOWN speed can be increased by the charge up circuit. From the state described above, FS1 becomes 1, and a current source of +22A is split off. Then, a CR charge/discharge circuit is formed, and the voltage at Pin 8 decreases with the time as shown in Fig. 1 below.
0V
Fig. 1. Voltage at Pin 8 when FS1 goes from 0 1 This time constant is obtained with the 50k resistance and an external capacitor. By alternating the commands between $02 and $03, the focus search voltage can be constructed. (Fig. 2)
0V
$
00 02
03
02
03
02
00
Fig. 2. Constructing the search voltage by alternating between $02 and $03. (Voltage at Pin 6)
- 29 -
CXA1992R
1-1. FS4 This switch is provided between the focus error input and the focus phase compensation, and is in charge of turning the focus servo ON and OFF. $00 $08 Focus off Focus on 1-2. Procedure of focus activation For description, suppose that the polarity is as described below. a) The lens is searching the disc from far to near; b) The output voltage (Pin 6) is changing from negative to positive; and c) The focus S-curve is varying as shown below.
A t
Fig. 3. S-curve The focus servo is activated at the operating point indicated by A in Fig. 3. Ordinarily, focus searching and the turning the focus servo switch ON are performed during the focus S-curve transits the point A indicated in Fig. 3. To prevent misoperation, this signal is ANDed with the focus OK signal. In this IC, FZC (Focus Zero Cross) signal is output from the SENS1 pin (Pin 25) as the point A transit signal. In addition, focus OK is output as a signal indicating that the signal is in focus (can be in focus in this case). Following the line of the above description, focusing can be well obtained by observing the following timing chart.
(20ms) (200ms) $02 ($00) $03 $08
Drive voltage
Focus error
The broken lines in the figure indicate the voltage assuming the signal is not in focus.
SENS1 (FZC) The instant when the signal is brought into focus.
Focus OK
Fig. 4. Focus ON timing chart - 30 -
CXA1992R
Note that the time from the High to Low transition of FZC to the time command $08 is asserted must be minimized. To do this, the software sequence shown in B is better than the sequence shown in A.
FZC ? YES
Transfer $08 NO
F. OK ? YES Transfer $08
F. OK ? NO YES FZC ? YES NO
NO
Latch
Latch
(A)
(B)
Fig. 5. Poor and good software command sequences
2. $1X (DFCT1 at SENS1 pin (Pin 25), DFCT2 at SENS2 pin (Pin 26)) These commands deal with switching TG1/TG2, brake circuit ON/OFF, and the sled kick output. The bit configuration is as follows: D7 0 D6 0 D5 0 D4 1 D3 D2 D1 D0
D1 (PS1) 0 0 1 1
D0 (PS0) 0 1 0 1
TG1, TG2 Break circuit ON/OFF ON/OFF
Sled kick height
TG1, TG2, TM7 The purpose of TG1 and TG2 is to switch the tracking servo gain Up/Normal. TG1 and TG2 are interlinked switches. The brake circuit (TM7) is to prevent the frequently occurred phenomena where the merely 10-track jump has been performed actually though a 100-track jump was intended to be done due to the extremely degraded actuator settling caused by the servo motor exceeding the linear range after a 100 or 10-track jump. For the prevention method, when the actuator travels radially; that is, when it traverses from the inner track to the outer track of the disc and vice versa, the brake circuit utilizes the fact that the phase relationship between the RF envelope and the tracking error is 180 out-of-phase to cut the unneeded portion of the tracking error and apply braking.
- 31 -
Relative value 1 2 3 4
Sled kick height
CXA1992R
[A] RF_I 32 [D] TZC 49 Waveform Shaping Envelope Detection
[B] Waveform Shaping [E] Edge Detection (Latch) CXA1992 (MIRR) [C] [F] [G] DQ CK
D2 TM7 Low: open High: make [H]
BRK
Fig. 6. TM7 movement during braking operation
From inner to outer track [A] [B] [C] [D] [E] [F] [G] [H]
From outer to inner track
("MIRR")
("TZC")
0V
Braking is applied from here.
Fig. 7. Internal waveform 3. $2X (TZC at SENS1 pin (Pin 25), MIRR at SENS2 pin (Pin 26)) These commands deal with turning the tracking servo and sled servo ON/OFF, and creating the jump pulse and fast forward pulse during access operations. D7 0 D6 0 D5 1 D4 0 D3 D2 D1 D0
Tracking control 00 off 01 Servo ON 10 F-JUMP 11 R-JUMP TM1, TM3, TM4,
Sled control 00 off 01 Servo ON 10 F-FAST FORWARD 11 R-FAST FORWARD TM2, TM5, TM6
- 32 -
CXA1992R
4. $3XX These commands mainly control the balance and gain control circuit switches used during automatic tracking adjustment and the bias circuit switch used during automatic focus bias adjustment. In the initial resetting state, BAL1 to BAL4 switches and TOG1 to TOG4 switches are ON. Also, the IFB1 to 6 switches are ON. * Balance adjustment The balance adjustment switches BAL1 to BAL4 can be controlled by setting D6 = 0 and D7 = 0. The switches are set using D0 to D3. At this time, SENS1 outputs BALH and SENS2 outputs BALL. Data is set by specifying switch conditions D0 to D3 and sending a latch pulse with D6 = 0 and D7 = 0. Sending a latch pulse with D6, D7 0 does not change the balance switch settings.
START
BAL1 to BAL4 Switch Control
C.OUT is the frequency high enough ? YES SENS1/2 Balance OK ?
NO
Adjustment Completed
Balance adjustment * Gain adjustment The gain adjustment switches TOG1 to TOG4 can be controlled by setting D6 = 1 and D7 = 0. These switches are set using D0 to D3. At this time, SENS1 outputs TGH and SENS2 outputs TGL. In a fashion similar to the method used with the balance adjustment, set the data by specifying switch conditions D0 to D3 and sending a latch pulse with D6 = 1 and D7 = 0.
START
TOG1 to TOG4 Switch control SENS1/2 GAIN OK ? NO YES Adjustment Completed
Gain adjustment - 33 -
CXA1992R
* Focus bias adjustment The focus bias adjustment switches IFB1 to 6 can be controlled by setting D6 = 0 and D7 = 1. The switches are set using D0 to D5. At this time, SENS1 outputs FOH and SENS2 outputs FOL. Data is set by specifying switch conditions D0 to D5 and sending a latch pulse with D6 = 0 and D7 = 1.
START
IFB1 to 6 Switch Control SENS1/2 BIAS OK ? YES Adjustment Completed
NO
Focus bias adjustment method
* TGFL The tracking gain can be switched by setting D5 with D6 = 1 and D7 = 0. The tracking gain is GAIN UP with D5 = 1 and NORMAL GAIN with D5 = 0. When using a pickup with a low tracking gain, the tracking gain can be raised by approximately 6dB by setting GAIN UP. (This command does not raise the gain during playback.) * LPC The laser power control circuit can be turned ON and OFF by setting D0 with D6 = 1 and D7 = 1. The circuit is ON with D0 = 1 and OFF with D0 = 0. * LPCL The laser power control limit can be switched between 10% and 30% by setting D1 with D6 = 1 and D7 = 1. The control limit is 10% with D1 = 0 and 30% with D1 = 1. * LDON The laser diode can be turned ON and OFF by setting D2 with D6 = 1 and D7 = 1. The laser diode is ON with D2 = 1 and OFF with D2 = 0.
- 34 -
CXA1992R
* ATSC The anti-shock function can be controlled by setting D3 with D6 = 1 and D7 = 1. This function is disabled with D3 = 1 and enabled with D3 = 0. At this time, SENS1 outputs ATSC. Even if ATSC is disabled, ATSC is output to SENS1. When an anti-shock signal is generated during the enable status, TG1 and TG2 switch to GAIN UP mode. (In the Block Diagram, TG1 is set to the side and TG2 is OFF. Even if TG1 and TG2 are NORMAL mode, they switch to GAIN UP mode in conjunction with ATSC.) When the anti-shock function is not used, Pin 48 (ATSC) should be connected to VC. * RDFCT2 DFCT2 can be reset by setting D4 with D6 = 1 and D7 = 1. DFCT2 is reset with D4 = 1. After a reset, High is held when DFCT1 rises. During $1X commands, DFCT2 is output from SENS2. DFCT2 operates even if DFCT is disabled. Whether or not DFCT rises at the proper timing for the microcomputer can also be confirmed. * INT The interruption (scratched disc) countermeasure circuit can be set to operating status by setting D5 with D6 = 1 and D7 = 1. This circuit is enabled when D5 = 1 and disabled when D5 = 0. Even if DFCT1 does not rise, this circuit is effective for scratched discs which cause MIRR to rise. When MIRR rises, the DFCT switch is routed through the low-pass filter. The interruption countermeasure circuit is forcibly turned OFF regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC or LOCK) Even if DFCT is disabled, the interruption countermeasure circuit operates when INT is enabled.
Parallel direct interface * LOCK (Sled overrun prevention circuit) This circuit operates when LOCK is low. When LOCK is low, the sled is OFF, and TG1 and TG2 are UP (TRACKING GAIN UP).
LOCK
SLED
TM2 SW: SLED ON
side TM2 SW: side SLED OFF
TRACKING GAIN NORMAL TG1 SW: TG2 ON
UP TG1 SW: TG2 OFF side
side
- 35 -
CXA1992R
CPU Serial Interface Timing Chart
DATA D0 tWCK CLK 1/fck tD tWL tCD D1 D2 tWCK D3 tSU D4 th D5 D6 D7 D0
XLT
(VCC = 3.0V) Item Clock frequency Clock pulse width Setup time Hold time Delay time Latch pulse width Data transfer interval Low level input voltage High level input voltage Symbol fck fwck 500 500 500 500 1000 1000 0.0 (VCC - VEE) x 0.9 (VCC - VEE) x 0.1 VCC Min. Typ. Max. 1 Unit MHz ns ns ns ns ns ns V V
tsu th tD tWL tCD
VIL VIH
- 36 -
System Control DATA (Pin 22) 8-bit transfer DATA SENS1 D1 D0 SENS2 D3 D2
Item
ADDRESS
D7
D6
D5
D4
FOCUS CONTROL -- FZC H (HIGH-Z) TG1, TG2 BRAKE 1 = ENABLE 0 = DISABLE SLED MODE 2 TZC DFCT1 DFCT2 SLED KICK + 2 SLED KICK + 1 1 = GAIN UP 0 = NORMAL TRACKING MODE 1
0
0
0
0
FS4 Focus 1 = ON 0 = OFF FS2 SRCH ON 1 = ON 0 = OFF FS2 SRCH UP 1 = UP 0 = DOWN
TRACKING CONTROL
0
0
0
1
TRACKING SLED MODE
0
0
1
0
MIRR
- 37 - D1 OFF ON FWD MOVE REV MOVE 1 1 1 0 0 1 0 0 D0
1 TRACKING MODE
2 SLED MODE
D3
D2
OFF
0
0
ON
0
1
FWD JUMP
1
0
REV JUMP
1
1
CXA1992R
DATA (Pin 22) 12-bit transfer DATA SENS1 D2 BAL3 1 = OFF 0 = ON TOG3 1 = OFF 0 = ON IFB3 1 = OFF 0 = ON LDON LPCL 1 = 30% 0 = 10% 1 = OFF 0 = ON IFB2 IFB1 1 = OFF 0 = ON LPC 1 = ON 0 = OFF ATSC H (HIGH-Z) FOH FOL 1 = OFF 0 = ON 1 = OFF 0 = ON TOG2 TOG1 TGH TGL 1 = OFF 0 = ON 1 = OFF 0 = ON BALH BAL2 BAL1 BALL D1 D0 SENS2 D5 DFCT BAL4 -- 1 = OFF 0 = ON TOG4 -- 1 = OFF 0 = ON IFB4 1 = OFF 0 = ON ATSC 0 1 = DISABLE 0 = ENABLE TGFL 1 1 = GAIN UP 0 = NORMAL IFB6 IFB5 1 = OFF 0 = ON RDFCT2 0 1 = OFF 0 = ON INT 1 1 = ENABLE 1 = RESET 1 = DISABLE 1 = ON 0 = DISABLE 0 = NORMAL 0 = ENABLE 0 = OFF D4 D3
Item
ADDRESS
D11 D10 D9
D8 D7
D6
E-F BALANCE
0
0
1
1
0
TRACKING GAIN
0
0
1
1
0
FOCUS BIAS
0
0
1
1
1
- 38 -
Others
0
0
1
1
1
Notes) * When ATSC is enabled, even if TG1 and TG2 are NORMAL mode, TG1 and TG2 switch to GAIN UP mode in conjunction with ATSC and LOCK. * INT is forcibly disabled regardless of the command when the tracking gain is increased. (including when the gain is increased by ATSC or LOCK) When reset * SENS1 = FZC * SENS2 = High (Hi-Z) * RDFCT2 = 1 (Reset) * IFB1 to IFB6 = 0 (switch ON) * TOG1 to TOG4 = 0 (switch ON) * BAL1 to BAL4 = 1 (switch ON) * Other data is "0".
CXA1992R
CXA1992R
Serial Data Truth Table Serial Data FOCUS CONTROL 0000 0000 0000 0001 0000 0010 0000 0011 0000 0100 0000 0101 0000 0110 0000 0111 0000 1000 0000 1001 0000 1010 0000 1011 0000 1100 0000 1101 0000 1110 0000 1111 $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F HEX FS4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Functions FS2 FS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes) * FS1 1: OFF 0: ON * FS2 1: ON 0: OFF * FS4 In the Block Diagram: 1:SW side 0:SW side
BRAK SLD KICK TRACKING CONTROL 0001 0000 0001 0001 0001 0010 0001 0011 0001 0100 0001 0101 0001 0110 0001 0111 0001 1000 0001 1001 0001 1010 0001 1011 0001 1100 0001 1101 0001 1110 0001 1111 $10 $11 $12 $13 $14 $15 $16 $17 $18 $19 $1A $1B $1C $1D $1E $1F TG1 Fig. 6 KICK KICK TG2 D2 +2 +1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Notes) * TG1 In the Block Diagram: 1:SW side 0:SW side * TG2 1: OFF 0: ON * BRAKE When D2 in Fig. 6 is: 1: 1 0: 0 * Sled kick height D1 0 0 1 1 D0 0 1 0 1 Relative value 1 2 3 4
- 39 -
CXA1992R
Serial Data TRACKING/SLED MODE 0010 0000 0010 0001 0010 0010 0010 0011 0010 0100 0010 0101 0010 0110 0010 0111 0010 1000 0010 1001 0010 1010 0010 1011 0010 1100 0010 1101 0010 1110 0010 1111
HEX
Function TM6 TM5 TM4 TM3 TM2 TM1
$20 $21 $22 $23 $24 $25 $26 $27 $28 $29 $2A $2B $2C $2D $2E $2F
0 0 0 1 0 0 0 1 0 0 0 1 0 0 0 1
0 0 1 0 0 0 1 0 0 0 1 0 0 0 1 0
0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1
0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0
0 1 0 0 0 1 0 0 0 1 0 0 0 1 0 0
0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0
Notes) * TM1/TM2 In the Block Diagram: 1:SW side 0:SW side * TM3/TM4/TM5/TM6 1: ON 0: OFF
- 40 -
CXA1992R
Serial Data $3XX 0011 0000 0000 0011 0000 0001 0011 0000 0010 0011 0000 0011 0011 0000 0100 0011 0000 0101 0011 0000 0110 0011 0000 0111 0011 0000 1000 0011 0000 1001 0011 0000 1010 0011 0000 1011 0011 0000 1100 0011 0000 1101 0011 0000 1110 0011 0000 1111 0011 0001 0000 0011 0001 0001 0011 0001 0010 0011 0001 0011 0011 0001 0100 0011 0001 0101 0011 0001 0110 0011 0001 0111 0011 0001 1000 0011 0001 1001 0011 0001 1010 0011 0001 1011 0011 0001 1100 0011 0001 1101 0011 0001 1110 0011 0001 1111 0011 0010 0000 0011 0010 0001 0011 0010 0010 0011 0010 0011 0011 0010 0100 0011 0010 0101 0011 0010 0110 0011 0010 0111 0011 0010 1000 0011 0010 1001 0011 0010 1010 0011 0010 1011 0011 0010 1100 0011 0010 1101 0011 0010 1110 0011 0010 1111
HEX
BAL SW TOG SW 43214321
TGFL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IFB SW 654321 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
INT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RDF ATSC LDON LPCL LPC DFCT CT2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E E D D D D D D D D D D D D D D D D
$300 $301 $302 $303 $304 $305 $306 $307 $308 $309 $30A $30B $30C $30D $30E $30F $310 $311 $312 $313 $314 $315 $316 $317 $318 $319 $31A $31B $31C $31D $31E $31F $320 $321 $322 $323 $324 $325 $326 $327 $328 $329 $32A $32B $32C $32D $32E $32F
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- --------
- 41 -
CXA1992R
Serial Data $3XX 0011 0011 0000 0011 0011 0001 0011 0011 0010 0011 0011 0011 0011 0011 0100 0011 0011 0101 0011 0011 0110 0011 0011 0111 0011 0011 1000 0011 0011 1001 0011 0011 1010 0011 0011 1011 0011 0011 1100 0011 0011 1101 0011 0011 1110 0011 0011 1111 0011 0100 0000 0011 0100 0001 0011 0100 0010 0011 0100 0011 0011 0100 0100 0011 0100 0101 0011 0100 0110 0011 0100 0111 0011 0100 1000 0011 0100 1001 0011 0100 1010 0011 0100 1011 0011 0100 1100 0011 0100 1101 0011 0100 1110 0011 0100 1111 0011 0101 0000 0011 0101 0001 0011 0101 0010 0011 0101 0011 0011 0101 0100 0011 0101 0101 0011 0101 0110 0011 0101 0111 0011 0101 1000 0011 0101 1001 0011 0101 1010 0011 0101 1011 0011 0101 1100 0011 0101 1101 0011 0101 1110 0011 0101 1111
HEX
BAL SW TOG SW 43214321
TGFL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
IFB SW 654321 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
INT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RDF ATSC LDON LPCL LPC DFCT CT2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- D D D D D D D D D D D D D D D D -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
$330 $331 $332 $333 $334 $335 $336 $337 $338 $339 $33A $33B $33C $33D $33E $33F $340 $341 $342 $343 $344 $345 $346 $347 $348 $349 $34A $34B $34C $34D $34E $34F $350 $351 $352 $353 $354 $355 $356 $357 $358 $359 $35A $35B $35C $35D $35E $35F
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- --------
- 42 -
CXA1992R
Serial Data $3XX 0011 0110 0000 0011 0110 0001 0011 0110 0010 0011 0110 0011 0011 0110 0100 0011 0110 0101 0011 0110 0110 0011 0110 0111 0011 0110 1000 0011 0110 1001 0011 0110 1010 0011 0110 1011 0011 0110 1100 0011 0110 1101 0011 0110 1110 0011 0110 1111 0011 0111 0000 0011 0111 0001 0011 0111 0010 0011 0111 0011 0011 0111 0100 0011 0111 0101 0011 0111 0110 0011 0111 0111 0011 0111 1000 0011 0111 1001 0011 0111 1010 0011 0111 1011 0011 0111 1100 0011 0111 1101 0011 0111 1110 0011 0111 1111 0011 1000 0000 0011 1000 0001 0011 1000 0010 0011 1000 0011 0011 1000 0100 0011 1000 0101 0011 1000 0110 0011 1000 0111 0011 1000 1000 0011 1000 1001 0011 1000 1010 0011 1000 1011 0011 1000 1100 0011 1000 1101 0011 1000 1110 0011 1000 1111
HEX
BAL SW TOG SW 43214321
TGFL 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IFB SW 654321 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
INT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RDF ATSC LDON LPCL LPC DFCT CT2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
$360 $361 $362 $363 $364 $365 $366 $367 $368 $369 $36A $36B $36C $36D $36E $36F $370 $371 $372 $373 $374 $375 $376 $377 $378 $379 $37A $37B $37C $37D $37E $37F $380 $381 $382 $383 $384 $385 $386 $387 $388 $389 $38A $38B $38C $38D $38E $38F
-------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- -------- --------
1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0
1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0
1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0
1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
-- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- --
- 43 -
CXA1992R
Serial Data $3XX 0011 1001 0000 0011 1001 0001 0011 1001 0010 0011 1001 0011 0011 1001 0100 0011 1001 0101 0011 1001 0110 0011 1001 0111 0011 1001 1000 0011 1001 1001 0011 1001 1010 0011 1001 1011 0011 1001 1100 0011 1001 1101 0011 1001 1110 0011 1001 1111 0011 1010 0000 0011 1010 0001 0011 1010 0010 0011 1010 0011 0011 1010 0100 0011 1010 0101 0011 1010 0110 0011 1010 0111 0011 1010 1000 0011 1010 1001 0011 1010 1010 0011 1010 1011 0011 1010 1100 0011 1010 1101 0011 1010 1110 0011 1010 1111 0011 1011 0000 0011 1011 0001 0011 1011 0010 0011 1011 0011 0011 1011 0100 0011 1011 0101 0011 1011 0110 0011 1011 0111 0011 1011 1000 0011 1011 1001 0011 1011 1010 0011 1011 1011 0011 1011 1100 0011 1011 1101 0011 1011 1110 0011 1011 1111
HEX
BAL SW TOG SW 43214321
TGFL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IFB SW 654321 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0
INT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
RDF ATSC LDON LPCL LPC DFCT CT2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
$390 $391 $392 $393 $394 $395 $396 $397 $398 $399 $39A $39B $39C $39D $39E $39F $3A0 $3A1 $3A2 $3A3 $3A4 $3A5 $3A6 $3A7 $3A8 $3A9 $3AA $3AB $3AC $3AD $3AE $3AF $3B0 $3B1 $3B2 $3B3 $3B4 $3B5 $3B6 $3B7 $3B8 $3B9 $3BA $3BB $3BC $3BD $3BE $3BF
-- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- --
- 44 -
CXA1992R
Serial Data $3XX 0011 1100 0000 0011 1100 0001 0011 1100 0010 0011 1100 0011 0011 1100 0100 0011 1100 0101 0011 1100 0110 0011 1100 0111 0011 1100 1000 0011 1100 1001 0011 1100 1010 0011 1100 1011 0011 1100 1100 0011 1100 1101 0011 1100 1110 0011 1100 1111 0011 1101 0000 0011 1101 0001 0011 1101 0010 0011 1101 0011 0011 1101 0100 0011 1101 0101 0011 1101 0110 0011 1101 0111 0011 1101 1000 0011 1101 1001 0011 1101 1010 0011 1101 1011 0011 1101 1100 0011 1101 1101 0011 1101 1110 0011 1101 1111 0011 1110 0000 0011 1110 0001 0011 1110 0010 0011 1110 0011 0011 1110 0100 0011 1110 0101 0011 1110 0110 0011 1110 0111 0011 1110 1000 0011 1110 1001 0011 1110 1010 0011 1110 1011 0011 1110 1100 0011 1110 1101 0011 1110 1110 0011 1110 1111
HEX
BAL SW TOG SW 43214321
TGFL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IFB SW 654321 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
INT 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RDF ATSC LDON LPCL LPC DFCT CT2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 E E E E E E E E D D D D D D D D E E E E E E E E D D D D D D D D E E E E E E E E D D D D D D D D 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
$3C0 $3C1 $3C2 $3C3 $3C4 $3C5 $3C6 $3C7 $3C8 $3C9 $3CA $3CB $3CC $3CD $3CE $3CF $3D0 $3D1 $3D2 $3D3 $3D4 $3D5 $3D6 $3D7 $3D8 $3D9 $3DA $3DB $3DC $3DD $3DE $3DF $3E0 $3E1 $3E2 $3E3 $3E4 $3E5 $3E6 $3E7 $3E8 $3E9 $3EA $3EB $3EC $3ED $3EE $3EF
-- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- --
- 45 -
CXA1992R
Serial Data $3XX 0011 1111 0000 0011 1111 0001 0011 1111 0010 0011 1111 0011 0011 1111 0100 0011 1111 0101 0011 1111 0110 0011 1111 0111 0011 1111 1000 0011 1111 1001 0011 1111 1010 0011 1111 1011 0011 1111 1100 0011 1111 1101 0011 1111 1110 0011 1111 1111
HEX
BAL SW TOG SW 43214321
TGFL -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
IFB SW 654321 ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------ ------------
INT 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1
RDF ATSC LDON LPCL LPC DFCT CT2 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 E E E E E E E E D D D D D D D D 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
$3F0 $3F1 $3F2 $3F3 $3F4 $3F5 $3F6 $3F7 $3F8 $3F9 $3FA $3FB $3FC $3FD $3FE $3FF
-- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- -- -- -- -- ---- -- -- --
Notes) * 0 means OFF and 1 means ON for TOG SW and BAL SW. These are not equal to the setting values of each bit for serial data. * "--" in the Truth Table indicates that the status does not change. * TGFL In the Block Diagram: 1:SW side 0:SW side * ATSC E: enable/D: disable * DFCT E: enable/D: disable
- 46 -
CXA1992R
Initial State (resetting state) Item FOCUS CONTROL TRACKING CONTROL TRACKING SLED MODE ADDRESS DATA HEX $00 $10 $20
D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
Item E-F BALANCE TRACKING GAIN FOCUS BIAS Others
ADDRESS
DATA
D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 1 1 0 1 0 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HEX $300 $340 $380 $3D0
The above data means the following operation modes. FOCUS CONTROL TRACKING CONTROL TRACKING SLED MODE E-F BALANCE TRACKING GAIN FOCUS BIAS Others : FOCUS OFF, FOCUS SEARCH OFF, FOCUS SEACH DOWN : TG1-TG2 NORMAL, BRAKE DISABLE, SLED KICK relative height value 1 : TRACKING OFF, SLED OFF : BAL1 to BAL4 = 0 (switch ON). DFCT ENABLE : TOG1 to TOG4 = 0 (switch ON), TGFL NORMAL : IFB1 to IFB6 = 0 (switch ON) : INT DISABLE, DFCT2 RESET, ATSC ENABLE, LDON OFF, LPCL 10%, LPC OFF
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CXA1992R
Notes on Operation 1. Focus OK circuit 1) Refer to the "Description of Operation" for the time constant setting of the focus OK amplifier LPF and the mirror amplifier HPF. 2) The equivalent circuit for the output pin (FOK) is shown in the diagram below.
VCC 20k FOK 40k 27 RL 100k VCC VEE VEE
The FOK and comparator output are as follows: Output voltage High : VFOKH near Vcc Output voltage Low : VFOKL Vsat (NPN) + VEE
2. Sled amplifier The sled amplifier may oscillate when used by the buffer amplifier. Use with a gain of approximately 20dB. 3. Focus/Tracking internal phase compensation and reference design material Item FCS 1.2kHz gain 1.2kHz phase 1.2kHz gain TRK 1.2kHz phase 2.7kHz gain 2.7kHz phase 08 08 25 25 25 13 25 13 13 CTGU = 0.1F SD Measurement pin 6 Conditions CFLB = 0.1F CFGD = 0.1F Typ. 21.5 63 13 -125 26.5 -130 Unit dB deg dB deg dB deg
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CXA1992R
Package Outline
Unit: mm
52PIN LQFP(PLASTIC)
12.0 0.2 10.0 0.1 39 40 27 26 B + 0.1 1.5 0 0.1
A 52 1 + 0.08 0.32 - 0.07 13 0.65 0.13 M 14
0.25
0.6 0.15
0.1 0.1
(11.0)
+ 0.08 0.32 - 0.07 (0.3)
0 to 10
DETAIL A
(0.5)
DETAIL B
NOTE: "" Dimensions do not include mold protrusion.
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-52P-L01 LQFP052-P-1010 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN PALLADIUM PLATING COPPER ALLOY 0.3g
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(0.125) + 0.04 0.145 - 0.025

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